With the continuous development of semiconductor technology, the critical dimension of semiconductor devices has become smaller and smaller, increasing the number of the semiconductor devices in a two-dimensional interconnect structure has become more and more difficult. Thus, three-dimensional packaging methods have been used to increase the integration level of semiconductor devices.
The three-dimensional packaging methods include the die stacking method and the package stacking method based on metal wire bonding, and the three-dimensional stacking method based on through silicon via (TSV) technique. The three-dimensional stacking method utilizing the TSV technique may have certain advantages, such as high integration level and significantly reduced interconnect length, etc. Thus, it is able to effectively solve the signal delay issue of the semiconductor devices in the two-dimensional system. Further, using the TSV technique may be able to integrate the modules with different functions, such as radio frequency module, memory module, logic module and the micro-electro-mechanical system, etc., to achieve the packaging process. Thus, the three-dimensional stacking method utilizing the TSV technique has become more and more important in the semiconductor packaging technology.
The fabrication process of a conductive plug structure based on the TSV technique includes providing a substrate; etching the substrate to form a contact hole in the substrate; forming an insulation layer on the inner side surfaces of the contact hole and the substrate; forming a conductive layer on the insulation layer and to fill the contact hole by a physical vapor deposition process or an electroplating process; and removing the conductive layer on the surface of the substrate by a chemical mechanical polishing process. The insulation layer is used to electrically insulate the subsequently formed conductive layer.
However, the performance of the conductive plug structure formed by such existing fabrication methods may not be as desired. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems in the art.